L-Edit Improvements

• TCL-based T-Cells
• Import Calibre rule sets into Interactive DRC

Enhanced SDL and Module Generator

• Schematic-driven placement
  • Relative position and rotation taken from schematic symbol
• HiPer DevGen
  • Differential pairs, current mirrors, MOSFETs and resistors
• SDL Router improvements
  • Single-layer ("river") routing
  • Double-via support

S-Edit Improvements

• Integrated Verilog-A and SPICE views
• User-defined netlisting priority of different views
• Spice Wizard added to "Additional SPICE Commands" dialog
• Model Explorer (S-Edit and T-Spice): view model and device parameters
  • Model names, versions, and information
  • Model parameters supplied in libraries
  • Device parameters supplied on instances
  • State variables calculated on instances

HiPer Verify Additions

• Additional commands
  • WITH NEIGHBOR is now supported
  • REGION CENTERLINE option for INT, EXT, ENC rules is now supported
• HiPer Extract enhancements
  • Labels devices by placing port opjects
  • Device and node counts are now written in the netlist

All New W-Edit

• W-Edit is not just a simulation results viewer, but a Waveform Analysis Platform
• Built-in measurements
• Scripting

HiPer DevGen Tool Offering

• T-Cell based device generation
• Differential Pairs
• Current Mirrors
• MOSFETs
• Resistors